Macros for packing and unpacking 3-D arrays in Verilog
I am a beginner with Verilog, I want to pack and unpack 3-D inputs and outputs in the code for which I have defined two macros as below:
`define PACK_3D(PK_WIDTH,PK_HEIGHT, PK_DEPTH, PK_SRC, PK_DEST)
genvar pk_idh;
genvar pk_idd;
generate for (pk_idd=0; pk_idd<(PK_DEPTH); pk_idd=pk_idd+1) begin
generate for (pk_idh=0; pk_idh<(PK_HEIGHT); pk_idh=pk_idh+1) begin
assign PK_DEST[pk_idd*(PK_HEIGHT*PK_WIDTH) + pk_idh*(PK_WIDTH) + (PK_WIDTH-1): pk_idd*(PK_HEIGHT*PK_WIDTH) + pk_idh*(PK_WIDTH)] = PK_SRC[pk_idd][pk_idh][(PK_WIDTH)-1):0];
end
endgenerate
end
endgenerate
`define UNPACK_3D(PK_WIDTH, PK_HEIGHT, PK_DEPTH, PK_SRC, PK_DEST)
genvar pk_idh;
genvar pk_idd;
generate for (pk_idd=0; pk_idd<(PK_DEPTH); pk_idd=pk_idd+1) begin
generate for (pk_idh=0; pk_idh<(PK_HEIGHT); pk_idh=pk_idh+1) begin
assign PK_DEST[pk_idd][pk_idh][(PK_WIDTH)-1):0] = PK_SRC[pk_idd*(PK_HEIGHT*PK_WIDTH) + pk_idh*(PK_WIDTH) + (PK_WIDTH-1): pk_idd*(PK_HEIGHT*PK_WIDTH) + pk_idh*(PK_WIDTH)];
end
endgenerate
end
endgenerate
Next, I have built an add module to add two 3-D matrices and return the output as below:
module add(clk, rst, g_input, e_input, o);
input clk,rst;
localparam num=4;
localparam h = 3;
localparam w = 3;
localparam d = 2;
input [2*num*h*w*d-1:0] g_input;
input [2*num*h*w*d-1:0] e_input;
output reg [2*num*h*w*d-1:0] o;
reg [2*num -1: 0] g_unpack[d-1:0][h-1:0][w-1:0];
reg [2*num -1: 0] e_unpack[d-1:0][h-1:0][w-1:0];
reg [2*num -1: 0] o_unpack[d-1:0][h-1:0][w-1:0];
`UNPACK_3D(w,h,d,g_input,g_unpack);
`UNPACK_3D(w,h,d,e_input,e_unpack);
integer i_d, i_h, i_w
always@* // always combinational block
begin
for (i_d = 0; i_d < d; i_d = i_d+1)
begin
for (i_h = 0; i_h < d; i_h = i_h+1)
begin
for (i_w = 0; i_w < d; i_w = i_w+1)
begin
o_unpack[i_d][i_h][i_w] = g_unpack[i_d][i_h][i_w] + e_unpack[i_d][i_h][i_w];
end
end
end
end
`PACK_3D(w,h,d,o_unpack,o);
endmodule
I got the idea from the this discussion. Although I when I try to compile the code above, I get a compilation error:
Error: ./add.v:43: Syntax error at or near token 'generate'
in macro "UNPACK_3D"
called from file "./add.v" (line 43). (VER-294)
Error: ./add.v:43: Syntax error at or near token '('
in macro "UNPACK_3D"
called from file "./add.v" (line 43). (VER-294)
Error: ./add.v:44: Syntax error at or near token 'generate'
in macro "UNPACK_3D"
called from file "./add.v" (line 44). (VER-294)
Error: ./add.v:44: Syntax error at or near token '('
in macro "UNPACK_3D"
called from file "./add.v" (line 44). (VER-294)
Error: ./add.v:44: Syntax error at or near token '('
in macro "UNPACK_3D"
called from file "./add.v" (line 44). (VER-294)
Error: ./add.v:48: Syntax error at or near token 'always'. (VER-294)
Error: ./add.v:50: Syntax error at or near token ';'. (VER-294)
Error: ./add.v:52: Syntax error at or near token ';'. (VER-294)
Error: ./add.v:54: Syntax error at or near token ';'. (VER-294)
Error: ./add.v:62: Syntax error at or near token 'generate'
in macro "PACK_3D"
called from file "./add.v" (line 62). (VER-294)
Error: ./add.v:62: Syntax error at or near token '('
in macro "PACK_3D"
called from file "./add.v" (line 62). (VER-294)
Error: ./add.v:62: Syntax error at or near token '('
in macro "PACK_3D"
called from file "./add.v" (line 62). (VER-294)
*** Presto compilation terminated with 12 errors. ***
Can anyone please help to resolve this?
Thank you.
compiler-errors verilog
add a comment |
I am a beginner with Verilog, I want to pack and unpack 3-D inputs and outputs in the code for which I have defined two macros as below:
`define PACK_3D(PK_WIDTH,PK_HEIGHT, PK_DEPTH, PK_SRC, PK_DEST)
genvar pk_idh;
genvar pk_idd;
generate for (pk_idd=0; pk_idd<(PK_DEPTH); pk_idd=pk_idd+1) begin
generate for (pk_idh=0; pk_idh<(PK_HEIGHT); pk_idh=pk_idh+1) begin
assign PK_DEST[pk_idd*(PK_HEIGHT*PK_WIDTH) + pk_idh*(PK_WIDTH) + (PK_WIDTH-1): pk_idd*(PK_HEIGHT*PK_WIDTH) + pk_idh*(PK_WIDTH)] = PK_SRC[pk_idd][pk_idh][(PK_WIDTH)-1):0];
end
endgenerate
end
endgenerate
`define UNPACK_3D(PK_WIDTH, PK_HEIGHT, PK_DEPTH, PK_SRC, PK_DEST)
genvar pk_idh;
genvar pk_idd;
generate for (pk_idd=0; pk_idd<(PK_DEPTH); pk_idd=pk_idd+1) begin
generate for (pk_idh=0; pk_idh<(PK_HEIGHT); pk_idh=pk_idh+1) begin
assign PK_DEST[pk_idd][pk_idh][(PK_WIDTH)-1):0] = PK_SRC[pk_idd*(PK_HEIGHT*PK_WIDTH) + pk_idh*(PK_WIDTH) + (PK_WIDTH-1): pk_idd*(PK_HEIGHT*PK_WIDTH) + pk_idh*(PK_WIDTH)];
end
endgenerate
end
endgenerate
Next, I have built an add module to add two 3-D matrices and return the output as below:
module add(clk, rst, g_input, e_input, o);
input clk,rst;
localparam num=4;
localparam h = 3;
localparam w = 3;
localparam d = 2;
input [2*num*h*w*d-1:0] g_input;
input [2*num*h*w*d-1:0] e_input;
output reg [2*num*h*w*d-1:0] o;
reg [2*num -1: 0] g_unpack[d-1:0][h-1:0][w-1:0];
reg [2*num -1: 0] e_unpack[d-1:0][h-1:0][w-1:0];
reg [2*num -1: 0] o_unpack[d-1:0][h-1:0][w-1:0];
`UNPACK_3D(w,h,d,g_input,g_unpack);
`UNPACK_3D(w,h,d,e_input,e_unpack);
integer i_d, i_h, i_w
always@* // always combinational block
begin
for (i_d = 0; i_d < d; i_d = i_d+1)
begin
for (i_h = 0; i_h < d; i_h = i_h+1)
begin
for (i_w = 0; i_w < d; i_w = i_w+1)
begin
o_unpack[i_d][i_h][i_w] = g_unpack[i_d][i_h][i_w] + e_unpack[i_d][i_h][i_w];
end
end
end
end
`PACK_3D(w,h,d,o_unpack,o);
endmodule
I got the idea from the this discussion. Although I when I try to compile the code above, I get a compilation error:
Error: ./add.v:43: Syntax error at or near token 'generate'
in macro "UNPACK_3D"
called from file "./add.v" (line 43). (VER-294)
Error: ./add.v:43: Syntax error at or near token '('
in macro "UNPACK_3D"
called from file "./add.v" (line 43). (VER-294)
Error: ./add.v:44: Syntax error at or near token 'generate'
in macro "UNPACK_3D"
called from file "./add.v" (line 44). (VER-294)
Error: ./add.v:44: Syntax error at or near token '('
in macro "UNPACK_3D"
called from file "./add.v" (line 44). (VER-294)
Error: ./add.v:44: Syntax error at or near token '('
in macro "UNPACK_3D"
called from file "./add.v" (line 44). (VER-294)
Error: ./add.v:48: Syntax error at or near token 'always'. (VER-294)
Error: ./add.v:50: Syntax error at or near token ';'. (VER-294)
Error: ./add.v:52: Syntax error at or near token ';'. (VER-294)
Error: ./add.v:54: Syntax error at or near token ';'. (VER-294)
Error: ./add.v:62: Syntax error at or near token 'generate'
in macro "PACK_3D"
called from file "./add.v" (line 62). (VER-294)
Error: ./add.v:62: Syntax error at or near token '('
in macro "PACK_3D"
called from file "./add.v" (line 62). (VER-294)
Error: ./add.v:62: Syntax error at or near token '('
in macro "PACK_3D"
called from file "./add.v" (line 62). (VER-294)
*** Presto compilation terminated with 12 errors. ***
Can anyone please help to resolve this?
Thank you.
compiler-errors verilog
add a comment |
I am a beginner with Verilog, I want to pack and unpack 3-D inputs and outputs in the code for which I have defined two macros as below:
`define PACK_3D(PK_WIDTH,PK_HEIGHT, PK_DEPTH, PK_SRC, PK_DEST)
genvar pk_idh;
genvar pk_idd;
generate for (pk_idd=0; pk_idd<(PK_DEPTH); pk_idd=pk_idd+1) begin
generate for (pk_idh=0; pk_idh<(PK_HEIGHT); pk_idh=pk_idh+1) begin
assign PK_DEST[pk_idd*(PK_HEIGHT*PK_WIDTH) + pk_idh*(PK_WIDTH) + (PK_WIDTH-1): pk_idd*(PK_HEIGHT*PK_WIDTH) + pk_idh*(PK_WIDTH)] = PK_SRC[pk_idd][pk_idh][(PK_WIDTH)-1):0];
end
endgenerate
end
endgenerate
`define UNPACK_3D(PK_WIDTH, PK_HEIGHT, PK_DEPTH, PK_SRC, PK_DEST)
genvar pk_idh;
genvar pk_idd;
generate for (pk_idd=0; pk_idd<(PK_DEPTH); pk_idd=pk_idd+1) begin
generate for (pk_idh=0; pk_idh<(PK_HEIGHT); pk_idh=pk_idh+1) begin
assign PK_DEST[pk_idd][pk_idh][(PK_WIDTH)-1):0] = PK_SRC[pk_idd*(PK_HEIGHT*PK_WIDTH) + pk_idh*(PK_WIDTH) + (PK_WIDTH-1): pk_idd*(PK_HEIGHT*PK_WIDTH) + pk_idh*(PK_WIDTH)];
end
endgenerate
end
endgenerate
Next, I have built an add module to add two 3-D matrices and return the output as below:
module add(clk, rst, g_input, e_input, o);
input clk,rst;
localparam num=4;
localparam h = 3;
localparam w = 3;
localparam d = 2;
input [2*num*h*w*d-1:0] g_input;
input [2*num*h*w*d-1:0] e_input;
output reg [2*num*h*w*d-1:0] o;
reg [2*num -1: 0] g_unpack[d-1:0][h-1:0][w-1:0];
reg [2*num -1: 0] e_unpack[d-1:0][h-1:0][w-1:0];
reg [2*num -1: 0] o_unpack[d-1:0][h-1:0][w-1:0];
`UNPACK_3D(w,h,d,g_input,g_unpack);
`UNPACK_3D(w,h,d,e_input,e_unpack);
integer i_d, i_h, i_w
always@* // always combinational block
begin
for (i_d = 0; i_d < d; i_d = i_d+1)
begin
for (i_h = 0; i_h < d; i_h = i_h+1)
begin
for (i_w = 0; i_w < d; i_w = i_w+1)
begin
o_unpack[i_d][i_h][i_w] = g_unpack[i_d][i_h][i_w] + e_unpack[i_d][i_h][i_w];
end
end
end
end
`PACK_3D(w,h,d,o_unpack,o);
endmodule
I got the idea from the this discussion. Although I when I try to compile the code above, I get a compilation error:
Error: ./add.v:43: Syntax error at or near token 'generate'
in macro "UNPACK_3D"
called from file "./add.v" (line 43). (VER-294)
Error: ./add.v:43: Syntax error at or near token '('
in macro "UNPACK_3D"
called from file "./add.v" (line 43). (VER-294)
Error: ./add.v:44: Syntax error at or near token 'generate'
in macro "UNPACK_3D"
called from file "./add.v" (line 44). (VER-294)
Error: ./add.v:44: Syntax error at or near token '('
in macro "UNPACK_3D"
called from file "./add.v" (line 44). (VER-294)
Error: ./add.v:44: Syntax error at or near token '('
in macro "UNPACK_3D"
called from file "./add.v" (line 44). (VER-294)
Error: ./add.v:48: Syntax error at or near token 'always'. (VER-294)
Error: ./add.v:50: Syntax error at or near token ';'. (VER-294)
Error: ./add.v:52: Syntax error at or near token ';'. (VER-294)
Error: ./add.v:54: Syntax error at or near token ';'. (VER-294)
Error: ./add.v:62: Syntax error at or near token 'generate'
in macro "PACK_3D"
called from file "./add.v" (line 62). (VER-294)
Error: ./add.v:62: Syntax error at or near token '('
in macro "PACK_3D"
called from file "./add.v" (line 62). (VER-294)
Error: ./add.v:62: Syntax error at or near token '('
in macro "PACK_3D"
called from file "./add.v" (line 62). (VER-294)
*** Presto compilation terminated with 12 errors. ***
Can anyone please help to resolve this?
Thank you.
compiler-errors verilog
I am a beginner with Verilog, I want to pack and unpack 3-D inputs and outputs in the code for which I have defined two macros as below:
`define PACK_3D(PK_WIDTH,PK_HEIGHT, PK_DEPTH, PK_SRC, PK_DEST)
genvar pk_idh;
genvar pk_idd;
generate for (pk_idd=0; pk_idd<(PK_DEPTH); pk_idd=pk_idd+1) begin
generate for (pk_idh=0; pk_idh<(PK_HEIGHT); pk_idh=pk_idh+1) begin
assign PK_DEST[pk_idd*(PK_HEIGHT*PK_WIDTH) + pk_idh*(PK_WIDTH) + (PK_WIDTH-1): pk_idd*(PK_HEIGHT*PK_WIDTH) + pk_idh*(PK_WIDTH)] = PK_SRC[pk_idd][pk_idh][(PK_WIDTH)-1):0];
end
endgenerate
end
endgenerate
`define UNPACK_3D(PK_WIDTH, PK_HEIGHT, PK_DEPTH, PK_SRC, PK_DEST)
genvar pk_idh;
genvar pk_idd;
generate for (pk_idd=0; pk_idd<(PK_DEPTH); pk_idd=pk_idd+1) begin
generate for (pk_idh=0; pk_idh<(PK_HEIGHT); pk_idh=pk_idh+1) begin
assign PK_DEST[pk_idd][pk_idh][(PK_WIDTH)-1):0] = PK_SRC[pk_idd*(PK_HEIGHT*PK_WIDTH) + pk_idh*(PK_WIDTH) + (PK_WIDTH-1): pk_idd*(PK_HEIGHT*PK_WIDTH) + pk_idh*(PK_WIDTH)];
end
endgenerate
end
endgenerate
Next, I have built an add module to add two 3-D matrices and return the output as below:
module add(clk, rst, g_input, e_input, o);
input clk,rst;
localparam num=4;
localparam h = 3;
localparam w = 3;
localparam d = 2;
input [2*num*h*w*d-1:0] g_input;
input [2*num*h*w*d-1:0] e_input;
output reg [2*num*h*w*d-1:0] o;
reg [2*num -1: 0] g_unpack[d-1:0][h-1:0][w-1:0];
reg [2*num -1: 0] e_unpack[d-1:0][h-1:0][w-1:0];
reg [2*num -1: 0] o_unpack[d-1:0][h-1:0][w-1:0];
`UNPACK_3D(w,h,d,g_input,g_unpack);
`UNPACK_3D(w,h,d,e_input,e_unpack);
integer i_d, i_h, i_w
always@* // always combinational block
begin
for (i_d = 0; i_d < d; i_d = i_d+1)
begin
for (i_h = 0; i_h < d; i_h = i_h+1)
begin
for (i_w = 0; i_w < d; i_w = i_w+1)
begin
o_unpack[i_d][i_h][i_w] = g_unpack[i_d][i_h][i_w] + e_unpack[i_d][i_h][i_w];
end
end
end
end
`PACK_3D(w,h,d,o_unpack,o);
endmodule
I got the idea from the this discussion. Although I when I try to compile the code above, I get a compilation error:
Error: ./add.v:43: Syntax error at or near token 'generate'
in macro "UNPACK_3D"
called from file "./add.v" (line 43). (VER-294)
Error: ./add.v:43: Syntax error at or near token '('
in macro "UNPACK_3D"
called from file "./add.v" (line 43). (VER-294)
Error: ./add.v:44: Syntax error at or near token 'generate'
in macro "UNPACK_3D"
called from file "./add.v" (line 44). (VER-294)
Error: ./add.v:44: Syntax error at or near token '('
in macro "UNPACK_3D"
called from file "./add.v" (line 44). (VER-294)
Error: ./add.v:44: Syntax error at or near token '('
in macro "UNPACK_3D"
called from file "./add.v" (line 44). (VER-294)
Error: ./add.v:48: Syntax error at or near token 'always'. (VER-294)
Error: ./add.v:50: Syntax error at or near token ';'. (VER-294)
Error: ./add.v:52: Syntax error at or near token ';'. (VER-294)
Error: ./add.v:54: Syntax error at or near token ';'. (VER-294)
Error: ./add.v:62: Syntax error at or near token 'generate'
in macro "PACK_3D"
called from file "./add.v" (line 62). (VER-294)
Error: ./add.v:62: Syntax error at or near token '('
in macro "PACK_3D"
called from file "./add.v" (line 62). (VER-294)
Error: ./add.v:62: Syntax error at or near token '('
in macro "PACK_3D"
called from file "./add.v" (line 62). (VER-294)
*** Presto compilation terminated with 12 errors. ***
Can anyone please help to resolve this?
Thank you.
compiler-errors verilog
compiler-errors verilog
edited Jan 19 at 11:52
Yash Kant
asked Jan 19 at 11:41
Yash KantYash Kant
86128
86128
add a comment |
add a comment |
1 Answer
1
active
oldest
votes
You have nested your generates
.
You should only have one generate..endgenerate
pair with both for
loops inside.
Also if you instance that code your genvars are declared twice ( genvar pk_idh; genvar pk_idd;
) Even if you make them different between pack and unpack, you can only call each macro once per module.
I would also recommend you first try the code without the macros. Then when the syntax is correct and the code works try to convert it to a macro.
Thanks, I'll try your suggestions and revert back.
– Yash Kant
Jan 19 at 12:05
You can eliminate allgenerate
/endgenerate
keywords. There were made optional in Verilog-2001.
– dave_59
Jan 19 at 16:07
add a comment |
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1 Answer
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active
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1 Answer
1
active
oldest
votes
active
oldest
votes
active
oldest
votes
You have nested your generates
.
You should only have one generate..endgenerate
pair with both for
loops inside.
Also if you instance that code your genvars are declared twice ( genvar pk_idh; genvar pk_idd;
) Even if you make them different between pack and unpack, you can only call each macro once per module.
I would also recommend you first try the code without the macros. Then when the syntax is correct and the code works try to convert it to a macro.
Thanks, I'll try your suggestions and revert back.
– Yash Kant
Jan 19 at 12:05
You can eliminate allgenerate
/endgenerate
keywords. There were made optional in Verilog-2001.
– dave_59
Jan 19 at 16:07
add a comment |
You have nested your generates
.
You should only have one generate..endgenerate
pair with both for
loops inside.
Also if you instance that code your genvars are declared twice ( genvar pk_idh; genvar pk_idd;
) Even if you make them different between pack and unpack, you can only call each macro once per module.
I would also recommend you first try the code without the macros. Then when the syntax is correct and the code works try to convert it to a macro.
Thanks, I'll try your suggestions and revert back.
– Yash Kant
Jan 19 at 12:05
You can eliminate allgenerate
/endgenerate
keywords. There were made optional in Verilog-2001.
– dave_59
Jan 19 at 16:07
add a comment |
You have nested your generates
.
You should only have one generate..endgenerate
pair with both for
loops inside.
Also if you instance that code your genvars are declared twice ( genvar pk_idh; genvar pk_idd;
) Even if you make them different between pack and unpack, you can only call each macro once per module.
I would also recommend you first try the code without the macros. Then when the syntax is correct and the code works try to convert it to a macro.
You have nested your generates
.
You should only have one generate..endgenerate
pair with both for
loops inside.
Also if you instance that code your genvars are declared twice ( genvar pk_idh; genvar pk_idd;
) Even if you make them different between pack and unpack, you can only call each macro once per module.
I would also recommend you first try the code without the macros. Then when the syntax is correct and the code works try to convert it to a macro.
answered Jan 19 at 12:03
OldfartOldfart
2,7372711
2,7372711
Thanks, I'll try your suggestions and revert back.
– Yash Kant
Jan 19 at 12:05
You can eliminate allgenerate
/endgenerate
keywords. There were made optional in Verilog-2001.
– dave_59
Jan 19 at 16:07
add a comment |
Thanks, I'll try your suggestions and revert back.
– Yash Kant
Jan 19 at 12:05
You can eliminate allgenerate
/endgenerate
keywords. There were made optional in Verilog-2001.
– dave_59
Jan 19 at 16:07
Thanks, I'll try your suggestions and revert back.
– Yash Kant
Jan 19 at 12:05
Thanks, I'll try your suggestions and revert back.
– Yash Kant
Jan 19 at 12:05
You can eliminate all
generate
/endgenerate
keywords. There were made optional in Verilog-2001.– dave_59
Jan 19 at 16:07
You can eliminate all
generate
/endgenerate
keywords. There were made optional in Verilog-2001.– dave_59
Jan 19 at 16:07
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