How is DMA cache coherency kept on Intel chipsets?












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I was reading something a few months ago about windows chipset iterations and PCH upgrades between them and I'm pretty sure I saw something on DMA cache coherency and that it involves the home agent or QHL but I can't find it now.



So I ask if anyone knows the details of any method of DMA cache coherency that has been employed by Intel and how it works.










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    I was reading something a few months ago about windows chipset iterations and PCH upgrades between them and I'm pretty sure I saw something on DMA cache coherency and that it involves the home agent or QHL but I can't find it now.



    So I ask if anyone knows the details of any method of DMA cache coherency that has been employed by Intel and how it works.










    share|improve this question

























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      0








      I was reading something a few months ago about windows chipset iterations and PCH upgrades between them and I'm pretty sure I saw something on DMA cache coherency and that it involves the home agent or QHL but I can't find it now.



      So I ask if anyone knows the details of any method of DMA cache coherency that has been employed by Intel and how it works.










      share|improve this question














      I was reading something a few months ago about windows chipset iterations and PCH upgrades between them and I'm pretty sure I saw something on DMA cache coherency and that it involves the home agent or QHL but I can't find it now.



      So I ask if anyone knows the details of any method of DMA cache coherency that has been employed by Intel and how it works.







      caching dma






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      share|improve this question











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      share|improve this question










      asked Jan 19 at 3:30









      Lewis KelseyLewis Kelsey

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